always @*
case (req_cs)
IDLE: if(tx_valid) begin
req_ns = VALID;
end
else begin
req_ns = IDLE;
end
VALID: req_ns = HOLD;
HOLD: if (tx_ready) begin
req_ns = DONE;
end
else begin
req_ns = HOLD;
end
DONE: if (tx_valid) begin
req_ns = VALID;
end
else begin
req_ns = IDLE;
end

default: req_ns = IDLE;
endcase

always @(posedge tx_clk or negedge tx_rstn) begin
if (~tx_rstn) begin
req <= 1'b0;
end
else if (req_ns == VALID) begin
req <= ~req;
end

end
always @(posedge tx_clk or negedge tx_rstn) begin
if (~tx_rstn) begin
req_sync3 <= 1'b0;
end
else begin
ack_sync3 <= ack_sync2;
end

end

assign ack_pulse = ack_sync2 ^ ack_sync3;
assign tx_ready = ack_pulse;

贴出了一部分handshak代码：
    tx_ready assert的条件是：检测到ack_sync2 的跳变沿
    req 翻转条件可以通过状态机来控制，状态机状态跳转会参考到tx_valid 以及 tx_ready 是否assert

希望可以帮到你~